The new modeling and simulation capability reduces development time for research and design validation teams working on early system prototyping and development of advanced multichannel applications. As a result, design and verification of electronic warfare systems and massive-MIMO systems for 5G is accelerated, which in turn enables faster deployment.
The integrated FPGA design flow enables system architects and FPGA engineers to download custom algorithms into Agilent digitizers with on-board FPGAs using built-in template designs and intellectual property cores with automatic push-button programming. The pre-defined FPGA interface template makes it easy to co-simulate real-time custom algorithms in the FPGA and top-level system modeling.
The W1462 SystemVue FPGA Architect is part of the SystemVue simulation environment. Updates to the W1462 software include:
- flexible hardware design entry with custom HDL and graphical schematic drawing using high-abstraction-level, primitive fixed-point blocks;
- vendor-agnostic HDL code generation and third-party HDL co-simulation; and
- a fully optimized and automated hardware implementation flow for leading-edge, high-performance digitization.
“SystemVue bridges a gap between high-performance user algorithms and real-time, measurement validation for multi-channel, gigahertz-wide applications like 5G and electronic warfare,” said Frank Ditore, Agilent EEsof EDA’s SystemVue product planner. “The new capability accelerates test development, while reducing the cost of narrowly-focused proprietary hardware platforms by using the open interfaces of commercial off-the-shelf system-level EDA software and superior test equipment.”
All interested parties are encouraged to enroll in the SystemVue Early Access Program at www.agilent.com/find/eesof-systemvue-earlyaccess.