Low-power ADC targets wireless sensor nodes

January 13, 2014 // By Peter Clarke
Researchers at the Public University of Navarra have developed an 8-bit charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) with a power consumption of 2-microwatts.

The ADC is intended for use in wireless sensor nodes (WSNs) where it could be used in a chip powered by energy harvested from the environment.

A paper describing the chip, written jointly by Antonio Lopez-Martin, a Professor of the Department of Electrical and Electronics Engineering at the University of Nevarra, and a telecommunications engineering student Inigo Cenoz-Villanueva, was selected the best paper at the 7th International Conference on Sensing Technology held in Wellington (New Zealand) in December.

The ADC employs an innovation in the capacitor switching procedure that is used within charge-redistribution SARs. In the paper simulation and measured results of a test chip operating at 100-ksamples per second show a spurious-free dynamic range of 55.63dB at a power consumption of 2.17-microwatts. The active area of the ADC is 0.275 square millimeters.

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