The LMK00334 creates four buffered copies of an input clock, while the LMK00338 produces eight buffered copies. They deliver 70 percent lower additive jitter and significantly higher supply noise rejection than competitive devices, providing system designers with ample jitter margin over the PCIe 3.0 specification. Both devices are supported in by the company's WEBENCH® Clock Architect to help simplify clock tree design for high-speed communications, networking, and data center systems, including servers, switches and routers.
The LMK00334 and LMK00338 claim to offer the lowest additive jitter at 30 fs at 100 MHz (PCIe 3.0) and 86 fs at 12 KHz to 20 MHz (HCSL at 156.25 MHz) to give designers more flexibility in timing budget allocation for the entire link. A high power supply rejection ratio (PSRR) of -75 dBc at 100 MHz provides improved jitter performance and better noise immunity than competitive devices, enabling robust signal integrity. Two universal inputs operate at up to 400 MHz and offer compatibility with any input type, including CML, LVPECL, LVDS, SSTL, HSTL, HCSL, or single-ended clocks and crystal oscillators.
The LMK00334 and LMK00338 can be combined with the CDCM9102 and the CDCM6208 PCIe clock generators to create a high-performance clock tree solution.
Engineers can accelerate their clock tree designs with the LMK00334 and LMK00338, by using WEBENCH® Clock Architect. It claims to be first timing design tool that can recommend and simulate a system clock tree solution from an exhaustive database of devices. The tool features phase-locked loop (PLL) filter design and the ability to simulate phase noise of the output clocks. It also provides the ability to simulate end-to-end jitter performance for the complete clock tree.
Both the LMK00334 and the LMK00338 utilize the LMK00338 evaluation module (EVM) to verify functionality and performance specifications. IBIS simulation models are also available for the LMK00334 and LMK00338.