Bit Error Ratio tester addresses multi-gigabit network design

January 21, 2014 // By Christoph Hammerschmidt
Developers and system integrators of multi-gigabit network equipment benefit from a Bit Error Ratio (BER) test solution introduced by Agilent Technologies. The M8000 enables them to characterize and validate Physical Layer designs and to perform compliance testing in this segment. Supporting a wide range of data rates and standards, the instrument helps accelerating insight into the performance margins of high-speed digital devices for computer, consumer, server, mobile computing and data center products.

When R&D and validation teams characterize next-generation designs, they face multiple test challenges. First, the faster data rates of the emerging next-generation digital computer buses, such as PCI Express 4 (with a bit rate of 16 GT/s) and USB 3.1 (with a bit rate of 10 Gb/s), present new signal integrity test challenges. New 128/130-bit and 128/132-bit coding formats complicate error detection and loopback pattern creation.

In addition, widespread adoption of mobile computing devices means more and more R&D and test engineers need to test different implementations of MIPI ports, with new data formats, termination models, multiple lanes and built-in error counting.

Lastly, with the enormous surge in data-center traffic, servers and storage designs must support much higher bandwidths on their backplane and networking ports. Data rates of 25 Gb/s and more on multiple lanes over PC boards, cable or optical interconnects are required by most industry standards, such as 100GbE, CEI and Fibre Channel. Testing such 25-Gb/s receiver ports requires new test capabilities to characterize device tolerance for interference, channel losses and crosstalk. The M8000 Series instruments enables R&D and test engineers to master these challenges, promises Agilent.

The first model in the new M8000 Series is the J-BERT M8020A. It enables fast and accurate receiver characterization of single- and multilane devices operating at data rates up to 16 Gb/s and 32 Gb/s. The M8020A accelerates insight into designs by:

  1. Streamlining receiver test setup by providing the highest level of integration. It offers built-in jitter injection, 8-tap de-emphasis, interference sources, reference clock multiplication, clock recovery and equalization.
  2. Ensuring accurate and repeatable measurements by automating in situ calibration of signal conditions.
  3. Reducing the effort required to bring devices into loopback test mode because the M8020A behaves like a link partner for the device under test and supports interactive link training for PCIe devices.

The J-BERT M8020A BERT is scalable and expandable to meet future test needs. It supports one to