Based around a high-density Xilinx Virtex-7 FPGA, the new module is aimed at LTE wireless front-end systems requiring multiple 10G CPRI links at up to rate option 8, as well as a range of other high-performance FPGA applications.
A selection of fast, flexible I/O is included, configured for wireless applications. An IDT CPS-1848 Serial RapidIO (SRIO) Gen 2 switch supports SRIO V2.1 at up to 20 Gbps per port. The board also includes three front panel SFP+ optical interfaces that provide flexible high-speed links, and are configurable as CPRI, OBSAI, GigE, SRIO or other standards.
An optional SRIO mini-SAS connector provides high-speed cabled connectivity. Timing and synchronisation is achieved via the front panel or backplane clock I/O, or optionally via GPS. No additional timing equipment is required, which reduces system complexity.
The Virtex-7 FPGA is provided as a VX415T-2 device as the standard build, with options up to the VX690T-2 available for the highest performance applications. It is provided with two banks of DDR3 SDRAM, and a bank of flash memory for storing FPGA configurations and additional software. Separate glue logic allows control, FPGA configuration and flash reprogramming over SRIO.
Available software includes a full Xilinx ISE/EDK example project, and MicroBlaze BSL including flash update. Where possible, this is all provided as source code, to give maximum flexibility. The board also contains embedded software for management and control.