eeTimes
eeTimes
eeTimes eeTimes EDN
Forgot password Register
Print - Send - -

New Products

Cadence drives giga-gate/gigahertz design at 28-nm with digital end-to-end flow

February 01, 2011 | Paul Buckley | 222901507
Cadence Design Systems, Inc. is advancing the design of giga-gate/gigahertz system on chips (SoCs) with a proven digital end-to-end flow at 28 nanometers that yields both performance and time-to-market advantages.
Driven by the Cadence Silicon Realization approach, the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. Working seamlessly with Cadence's analog/mixed-signal and silicon/package co-design domains, the new digital 28-nanometer flow enables designers to consider the entire chip flow holistically to drive breakthroughs in high-performance, low-power, mixed-signal, and even 3D-IC designs- critical success factors for mobility-based and multimedia SoCs.     

The new flow, available immediately, supports Cadence's approach to Silicon Realization through its focus on unique and pervasive design intent, abstraction, and convergence from RTL to GDSII, then through to packaging. Silicon Realization is a key element of the EDA360 vision.     

Eliminating the need for tradeoffs between complexity and advanced process nodes, the new flow optimizes complex design at 28 nanometers, providing a path for advanced SoC development to realize the cost benefits of smaller geometries. Key to the flow's performance (add link to Wei Lii's blog) is a unified digital design, implementation, and verification based on intent, abstraction, and convergence.     

“The complexity of 28-nanometer design coupled with the need to support complex giga-gate/gigahertz requirements demands an integrated end-to-end flow,” said David Desharnais, senior director, Silicon Realization product marketing. “Our unique Silicon Realization approach allows our customers to push their SoC designs to new levels in order to deliver the highest performance silicon for multimedia, communications and computing applications. Today's announcement of our comprehensive 28-nanometer digital Silicon Realization flow continues our push toward realizing the EDA360 vision.”     

The Encounter-based Silicon Realization digital end-to-end flow includes technologies such as Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, Cadence QRC Extraction, Encounter Power System and Encounter DFM technologies.
  
For further information: www.cadence.com.









Please login to post your comment - click here
Related News
MOST POPULAR NEWS
Interview
Technical papers

All material on this site Copyright © 2009 - 2010 European Business Press SA. All rights reserved.
This site contains articles under license from EETimes Group , a division of United Business Media LLC.